The Z80 Instruction Set

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What is an “Instruction Set” ?

“The instruction set, also called ISA (instruction set architecture), is part of a computer that pertains to programming, [ which is more or less ] ¹ machine language. The instruction set provides commands to the processor, to tell it what it needs to do. The instruction set consists of addressing modes, instructions, native data types, registers, memory architecture, interrupts, and exception handling, and external I/O“
Source:   Computerhope

“Sometimes referred to as machine code or Object code, machine language is a collection of binary digits or bits that the computer reads and interprets. Machine language is the only language a computer is capable of understanding“    Source:   Computerhope

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ADC A, s
Add accumulator and specified operand with carry

ADC HL, ss
Add with carry HL and register pair ss

ADD A, (HL)
Add accumulator with indirectly addressed memory location (HL)

DH: “Add the contents of where HL is pointing, to A”

ADD A, (IX + d)
Add accumulator with indexed addressed memory location (IX + d)

DH: “Add the contents of where IX+d is pointing, to A”

ADD A, (IY + d)
Add accumulator with indexed addressed memory location (IY + d)

DH: “Add the contents of where IY+d is pointing, to A”

ADD A,n
Add accumulator with immediate data n

ADD A, r
Add accumulator with register r

ADD HL, ss
Add HL and register pair ss

ADD IX, rr
Add IX with register pair rr

ADD IY, rr
Add IY and register pair rr

AND s
Logical AND accumulator with operand s

BIT b, (HL)
Test bit b of indirectly addressed memory location (HL)

BIT b, (IX + d)
Test bit b of indexed addressed memory location (IX + d)

BIT b, (IY + d)
Test bit b of the indexed addressed memory location (IY + d)

BIT b, r
Test bit b of register r

CALL cc,pq
Call subroutine on condition

CALL pq
Call subroutine at location pq

CCF
Compliment carry flag

CP s
Compare operand s to accumulator

CPD
Compare with decrement

CPDR
Block compare with decrement

CPI
Compare with increment

DI
Disable interrupts

LD dd, nn
Load register pair dd with immediate data nn

CPIR
Block compare with increment

CPL
Complement accumulator

DAA
Decimal adjust accumulator

DEC IX
Decrement IX

dec-iy DEC IY
Decrement IY

DEC m
Decrement operand m

DEC rr
Decrement register pair rr

DJNZ e
Decrement B and jump e relative on no zero

EI
Enable interrupts

EX (SP),HL
Exchange HL with top of stack

EX (SP),IX
Exchange IX with top of stack

EX (SP),IY
Exchange IY with top of stack

EX AF,AF'
Exchange accumulator and flags with alternate registers

EX DE,HL
Exchange the HL and DE registers

EXX
Exchange alternate registers

HALT
Halt CPU

IM 0
Set interrupt mode 0 condition

IM 1
Set interrupt mode 1 condition

IM 2
Set interrupt mode 2 condition

IN A, (N)
Load accumulator from input port N

IN r, (C)
Load register r from port(C)

INC (HL)
Increment indirectly addressed memory location (HL)

INC (IX+d)
Increment indexed addressed memory location (IX+d)

INC (IY+d)
Increment indexed addressed memory location (IY+d)

INC IX
Increment IX

INC IY
Increment IY

INC r
Increment register r

INC rr
Increment register pair rr

IND
Input with decrement

INDR
Block input with decrement

INI
Input with increment

INIR
Block input with increment

JP (HL)
Jump to HL

JP (IX)
Jump to IX

JP (IY)
Jump to IY

JP cc,pq
Jump on condition to location pq

JP pq
Jump to location pq

JR cc, e
Jump e relative on condition

JR e
Jump e relative

LD (BC),A
Load indirectly addressed memory location (BC) from the accumulator

LD (DE),A
Load indirectly addressed memory location (DE) from the accumulator

LD (HL),n
Load immediate data n into the indirectly addressed memory location (HL)

LD (HL),r
Load indirectly addressed memory location (HL) from register r

LD (IX+d),n
Load indexed addressed memory location (IX+d) with immediate data n

ld-dd-nn LD dd, (nn)
Load register pair dd from memory locations addressed by nn

LD dd,nn
Load register pair dd with immediate data nn

LD r, (IX+d)

LD r, (IX+d)
Load register r indirect from indexed memory location (IX+d)

LD r, (IY+d)

LD r, (IY+d)
Load register r indirect from indexed memory location (IY+d)

LD r, r’

LD r, r'
Load register r from register r’

LD r, n

LD r, n
Load register r with immediate data n

sddsds

sdsdsd

sdgdfdfgb

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Image#1: Taken from the Zilog Z80 CPU User Manual